1. Field of the Invention
The present invention relates to a device and a method of breaking leakage current path of a memory device and a structure of the memory device.
2. Description of the Related Art
Traditionally, the semiconductor memory may be classified into a non-volatile memory and a volatile memory.
The non-volatile memory can still retain the data even when the power is off. In contrast, in the volatile memory, such as static random access memory (SRAM) and dynamic random access memory (DRAM), the data is lost when the power is off.
As to the volatile memory, because SRAM is constructed by transistors, the speed of SRAM is about five times faster than the speed of DRAM. However, the cost and size of SRAM are respectively higher and larger than that of the DRAM. Therefore, in considerations of cost and size, DRAM is most widely used volatile memory. DRAM uses capacitors for storing data. Because of charge leakage from the capacitors, a refresh operation is required for recharging the capacitors. Therefore, if the power is turned off, the data stored therein will be lost. Even when the power is normally supplied, the data will gradually disappear because of the charge leakage of the capacitors. Therefore, the refresh operation is required.
Basically, a memory cell of DRAM comprises a transistor and a capacitor. Referring to FIG. 1, a schematic drawing a memory cell of DRAM is shown, wherein the capacitor is provided for storing charges to determine whether a logic state “1” or “0” is stored therein. Since the integration and density of DRAM cells are increased gradually, the defects occuring from the manufacturing process of the DRAM cells or due to the shorting between the cells can behardly prevented. Referring to FIG. 1, a traditional DRAM array includes memory cells 102 and 104 and a sense amplifier 106, wherein when a short of the bit line BLL and word line WLL of the memory cell 102 occurs at point A, a leakage current F is resulted. That is, the leakage current F will result in current leakage from the power supplying terminal VBLEQ via the bit line BLL of the memory cell 102 to the ground of the capacitor. When the memory is in standby state, the leakage current consumes a lot of power. Therefore, the longer the standby state, the more the consumption of power is.
Generally, in order to maintain a high signal-to-noise ratio (S/N ration), the leakage current can not be reduced by reducing the capacitance of the capacitor. The leakage current, in general, is about 300 μA for each current leakage path. Therefore, a conventional method to resolve the issue was proposed. FIG. 2 is a schematic drawing illustrating another conventional memory cell of DRAM. Referring to FIG. 2, a current limiting device, such as a depletion type NMOS transistor with low threshold voltage, is connected to the bit line pre-charger circuit of the memory cell 102 for reducing the leakage current. By using the current limiting device, the leakage current can be reduced up to about 15 μA for each current leakage path.
However, the disadvantage of the current limiting device is that even when the defective memory cell is replaced by a redundancy memory cell, the leakage current still exists and the period of pre-charging will be extended. More seriously, the leakage current is proportional to the number of the defective cells. For the portable electronic devices, the leakage current will drastically reduce the time of standby state of the battery, resulting in reduction of the speed of the memory and increase of the temperature of the device. Therefore, a device and a method for breaking current leakage path are highly desirable.